# 使用 Homebrew, apk, apt, dnf, Nix, pacman, scoop 安装 yosys 查看 yosys 的安装路径、可执行文件、元数据以及面向 AI 代理工作流的安全说明。 ## 安装 ```sh sudo av install brew:yosys ``` 其他安装命令: ### macOS - Homebrew (100%): ```sh brew install yosys ``` 证据: local Homebrew formula metadata ### Linux - apk (92%): ```sh sudo apk add yosys ``` 证据: Alpine Linux edge package indexes: yosys from https://dl-cdn.alpinelinux.org/alpine/edge/testing/x86_64/APKINDEX.tar.gz - Debian apt (92%): ```sh sudo apt install yosys ``` 证据: Debian stable package indexes: yosys from https://deb.debian.org/debian/dists/stable/main/binary-amd64/Packages.xz - dnf (92%): ```sh sudo dnf install yosys ``` 证据: Fedora Rawhide package metadata: yosys from https://dl.fedoraproject.org/pub/fedora/linux/development/rawhide/Everything/x86_64/os/repodata/07190dc5ae9f35ae73866675fed6d95fe6e8d9fe22c9d7cdf85862cb2ed24a4c-primary.xml.zst - Nix (92%): ```sh nix profile install nixpkgs#yosys ``` 证据: nixpkgs package indexes: pkgs/by-name/yo/yosys/package.nix from https://api.github.com/repos/NixOS/nixpkgs/git/trees/master?recursive=1 - pacman (92%): ```sh sudo pacman -S yosys ``` 证据: Arch Linux sync databases: yosys from https://geo.mirror.pkgbuild.com/extra/os/x86_64/extra.db.tar.gz ### Windows - Scoop (92%): ```sh scoop install main/yosys ``` 证据: Scoop official bucket manifest trees: bucket/yosys.json from https://api.github.com/repos/ScoopInstaller/Main/git/trees/master?recursive=1 ## 软件包事实 - **软件包键:** brew:yosys - **软件包管理器:** Homebrew - **版本:** 0.67 - **来源摘要:** Framework for Verilog RTL synthesis - **主页:** - **仓库:** - **最后更新:** 2026-07-13T05:24:20Z - **已生成:** 2026-08-03T19:37:03+00:00 ## 可执行文件 - yosys (别名) - yosys-abc (别名) - yosys-config (别名) - yosys-filterlib (别名) - yosys-smtbmc (别名) - yosys-witness (别名) ## 安装行为 - Bottle: 不可用 ## 版本和新鲜度 - 页面生成时间: 2026-08-03 - 管理器版本: 0.67 ## 项目历史与用法 Yosys is the open-source RTL synthesis framework that made Verilog synthesis scriptable, inspectable, and packageable in the same way compilers and Unix development tools are. It reads HDL, transforms designs through passes over RTLIL, maps logic with tools such as ABC, and writes netlists or interchange formats for FPGA, ASIC, and formal flows. ### 项目历史 Yosys began as Claire Wolf's BSc thesis project to support synthesis for a coarse-grained reconfigurable architecture, then expanded into general infrastructure for synthesis research. The Yosys documentation preserves that origin and describes the first documentation as a bachelor thesis at Vienna University of Technology. The 2013 Austrochip paper framed the problem plainly: commercial ASIC and FPGA tools dominated synthesis, but closed internals and encrypted intermediate formats made them poor bases for research and reproducibility. Yosys answered that gap with an extensible open framework: frontends convert HDL into RTLIL, passes transform and analyze it, and backends write the resulting design. By the late 2010s Yosys had moved from research artifact to central open hardware infrastructure. Contemporary documentation describes full support for the synthesizable subset of Verilog-2005, use in hobbyist, academic, and commercial settings, and a role in open FPGA and ASIC flows. YosysHQ now maintains Yosys and related tools, with commercial extensions available through Tabby CAD Suite while the open tool remains the ecosystem core. ### 采用历史 Yosys adoption followed the needs of open hardware. It became the synthesis engine in flows where proprietary vendor tools were unavailable, undesirable, or too opaque: Lattice iCE40/ECP5 flows with nextpnr, OpenLane/SkyWater open ASIC experiments, formal verification frontends, and education/research workflows that needed reproducible tooling. AB Open described Yosys as first launched in 2012 and as the first full-featured open-source package for Verilog HDL synthesis. That claim captures why it mattered: before Yosys, open-source HDL tooling had simulators and pieces of logic optimization, but not a broadly useful, scriptable Verilog synthesis framework packaged for everyday developers. Its adoption also comes from being a framework rather than a single hard-coded flow. Users can run the interactive shell, write synthesis scripts, add passes, target multiple FPGA families, emit formal solver formats, and combine it with related YosysHQ tools such as SBY, EQY, MCY, and SCY. ### 使用方式 Typical use starts with reading Verilog or SystemVerilog, checking hierarchy, running passes such as proc, opt, fsm, memory, techmap, and abc, then writing Verilog, BLIF, JSON, BTOR, SMT2, or another backend format. The README emphasizes both interactive use and script files, which made synthesis flows reviewable and reproducible. For FPGA work, Yosys handles synthesis while nextpnr or vendor tools handle place-and-route. For ASIC-style open flows, Yosys performs the synthesis portion before later physical-design stages. For formal workflows, it converts HDL into solver-oriented representations and underpins tools such as SBY. Package-manager users install it as a command-line suite: yosys for the shell and scripts, yosys-config for build integration, yosys-smtbmc for model checking workflows, and auxiliary binaries such as yosys-abc where packaged. ### 为什么软件包爱好者会关心 Yosys is one of the clearest examples of package managers changing who can participate in hardware design. A synthesis tool that once would have meant vendor installers and license servers can be installed, scripted, pinned in CI, built from source, and combined with other open packages. It also made hardware compilation feel more like software compilation: inspectable intermediate representations, pass pipelines, text scripts, plugins, tests, and reproducible command-line output. That is why package collections treat it as core developer tooling rather than as an exotic EDA side package. ### 时间线 - 2012: Yosys is publicly launched as an open Verilog synthesis suite. - 2013: The Yosys thesis/paper documents its design, RTLIL flow, extensibility, and reproducibility motivation. - 2018: Public coverage describes Yosys as a popular open synthesis framework with growing platform support. - 2020s: Yosys becomes central to open FPGA flows, OpenLane-style open ASIC work, and YosysHQ formal tools. ### Related projects - Berkeley ABC is used by Yosys for combinational logic minimization and technology mapping. - nextpnr is the open place-and-route tool commonly paired with Yosys for FPGA bitstream flows. - OpenLane uses Yosys for the synthesis stage in open ASIC flows. - SBY, EQY, MCY, and SCY are YosysHQ tools built around Yosys for formal verification, equivalence checking, mutation coverage, and trace workflows. - OSS CAD Suite and Tabby CAD Suite distribute Yosys with related open and commercial EDA tooling. ### 来源 - - - - - - ## 安全说明 没有找到 yosys 的匹配本地密钥处理 manifest。Nucleus 软件包元数据仍在此发布，以便未来覆盖拥有稳定的软件包 URL。 ## 其他软件包管理器记录 - Debian apt - yosys - 0.52-2: normalized package name match | Debian stable package indexes: yosys from https://deb.debian.org/debian/dists/stable/main/binary-amd64/Packages.xz | Framework for Verilog RTL synthesis | https://github.com/YosysHQ/yosys - Debian apt - yosys-abc - 0.52-2: normalized package name match | Debian stable package indexes: yosys-abc from https://deb.debian.org/debian/dists/stable/main/binary-amd64/Packages.xz | Sequential Logic Synthesis and Verification Algorithms | https://github.com/YosysHQ/yosys - Debian apt - yosys-dev - 0.52-2: normalized package name match | Debian stable package indexes: yosys-dev from https://deb.debian.org/debian/dists/stable/main/binary-amd64/Packages.xz | Framework for Verilog RTL synthesis (development files) | https://github.com/YosysHQ/yosys - Debian apt - yosys-doc - 0.52-2: normalized package name match | Debian stable package indexes: yosys-doc from https://deb.debian.org/debian/dists/stable/main/binary-amd64/Packages.xz | Framework for Verilog RTL synthesis (documentation) | https://github.com/YosysHQ/yosys - Nix - yosys: normalized package name match | nixpkgs package indexes: pkgs/by-name/yo/yosys/package.nix from https://api.github.com/repos/NixOS/nixpkgs/git/trees/master?recursive=1 - Ubuntu apt - yosys - 0.33-5build2: normalized package name match | Ubuntu 24.04 LTS package indexes: yosys from https://archive.ubuntu.com/ubuntu/dists/noble/universe/binary-amd64/Packages.gz | Framework for Verilog RTL synthesis | https://github.com/YosysHQ/yosys - Ubuntu apt - yosys-abc - 0.33-5build2: normalized package name match | Ubuntu 24.04 LTS package indexes: yosys-abc from https://archive.ubuntu.com/ubuntu/dists/noble/universe/binary-amd64/Packages.gz | Sequential Logic Synthesis and Verification Algorithms | https://github.com/YosysHQ/yosys - Ubuntu apt - yosys-dev - 0.33-5build2: normalized package name match | Ubuntu 24.04 LTS package indexes: yosys-dev from https://archive.ubuntu.com/ubuntu/dists/noble/universe/binary-amd64/Packages.gz | Framework for Verilog RTL synthesis (development files) | https://github.com/YosysHQ/yosys - Ubuntu apt - yosys-doc - 0.33-5build2: normalized package name match | Ubuntu 24.04 LTS package indexes: yosys-doc from https://archive.ubuntu.com/ubuntu/dists/noble/universe/binary-amd64/Packages.gz | Framework for Verilog RTL synthesis (documentation) | https://github.com/YosysHQ/yosys - apk - py3-yosys - 0.66-r0: normalized package name match | Alpine Linux edge package indexes: py3-yosys from https://dl-cdn.alpinelinux.org/alpine/edge/testing/x86_64/APKINDEX.tar.gz | Yosys Open SYnthesis Suite (python module) | https://yosyshq.net - apk - yosys - 0.66-r0: normalized package name match | Alpine Linux edge package indexes: yosys from https://dl-cdn.alpinelinux.org/alpine/edge/testing/x86_64/APKINDEX.tar.gz | Yosys Open SYnthesis Suite | https://yosyshq.net - apk - yosys-dev - 0.66-r0: normalized package name match | Alpine Linux edge package indexes: yosys-dev from https://dl-cdn.alpinelinux.org/alpine/edge/testing/x86_64/APKINDEX.tar.gz | Yosys Open SYnthesis Suite (development files) | https://yosyshq.net - dnf - yosys - 0.67-3.20260713git22c15a7.fc45: normalized package name match | Fedora Rawhide package metadata: yosys from https://dl.fedoraproject.org/pub/fedora/linux/development/rawhide/Everything/x86_64/os/repodata/07190dc5ae9f35ae73866675fed6d95fe6e8d9fe22c9d7cdf85862cb2ed24a4c-primary.xml.zst | Yosys Open SYnthesis Suite, including Verilog synthesizer | http://www.clifford.at/yosys/ - dnf - yosys-devel - 0.67-3.20260713git22c15a7.fc45: normalized package name match | Fedora Rawhide package metadata: yosys-devel from https://dl.fedoraproject.org/pub/fedora/linux/development/rawhide/Everything/x86_64/os/repodata/07190dc5ae9f35ae73866675fed6d95fe6e8d9fe22c9d7cdf85862cb2ed24a4c-primary.xml.zst | Development files to build Yosys synthesizer plugins | http://www.clifford.at/yosys/ - dnf - yosys-doc - 0.67-3.20260713git22c15a7.fc45: normalized package name match | Fedora Rawhide package metadata: yosys-doc from https://dl.fedoraproject.org/pub/fedora/linux/development/rawhide/Everything/x86_64/os/repodata/07190dc5ae9f35ae73866675fed6d95fe6e8d9fe22c9d7cdf85862cb2ed24a4c-primary.xml.zst | Documentation for Yosys synthesizer | http://www.clifford.at/yosys/ - dnf - yosys-share - 0.67-3.20260713git22c15a7.fc45: normalized package name match | Fedora Rawhide package metadata: yosys-share from https://dl.fedoraproject.org/pub/fedora/linux/development/rawhide/Everything/x86_64/os/repodata/07190dc5ae9f35ae73866675fed6d95fe6e8d9fe22c9d7cdf85862cb2ed24a4c-primary.xml.zst | Architecture-independent Yosys files | http://www.clifford.at/yosys/ ## Combined YAML source View the package source record on GitHub. [combined/yosys.yml](https://github.com/mxcl/pkgdb/blob/main/combined/yosys.yml) ## 来源 - pkg.so package database - Geiger risk classifier - curated package history - pkgdb category and tag curation - external package-manager database matches - cross-ecosystem install command graph