# 使用 Homebrew 安装 sv2v

查看 sv2v 的安装路径、可执行文件、元数据以及面向 AI 代理工作流的安全说明。

## 安装

```sh
sudo av install brew:sv2v
```

其他安装命令:

### macOS

- Homebrew (100%):

```sh
brew install sv2v
```

  证据: local Homebrew formula metadata

## 软件包事实

- **软件包键:** brew:sv2v
- **软件包管理器:** Homebrew
- **版本:** 0.0.13
- **来源摘要:** SystemVerilog to Verilog conversion
- **主页:** <https://github.com/zachjs/sv2v>
- **仓库:** <https://github.com/zachjs/sv2v>
- **最后更新:** 2026-07-22T13:39:31Z
- **已生成:** 2026-08-03T19:37:03+00:00

## 可执行文件

- sv2v (别名)

## 安装行为

- Bottle: 不可用

## 版本和新鲜度

- 页面生成时间: 2026-08-03
- 管理器版本: 0.0.13
## 项目历史与用法

sv2v is a command-line SystemVerilog-to-Verilog converter aimed at synthesizable hardware designs. It belongs to the open-source EDA toolchain culture around Yosys, where file-format and language-compatibility bridges are often packaged as small, scriptable tools.

### 项目历史

The README says the project was created to provide a completely free and open-source SystemVerilog-to-Verilog converter, because existing approaches were often commercial or limited in scope. It was originally developed to target Yosys and to pass through SystemVerilog features that Yosys already supported.

The README also places the idea in a Carnegie Mellon University open-hardware research project, with collaboration beginning in January 2019. The GitHub commit history's oldest page records an initial commit on February 8, 2019, as a fork of Tom Hawkin's Verilog parser.

### 采用历史

sv2v's adoption is niche but meaningful in open hardware workflows. The repository publishes prebuilt binaries for Ubuntu, macOS, and Windows, has a release series from v0.0.1 in January 2020 through v0.0.13 in March 2025, and is packaged in Homebrew according to the input facts.

### 使用方式

Typical use is to pass SystemVerilog source files to `sv2v` and receive converted Verilog on standard output or write adjacent `.v` files. The README emphasizes passing all source files together so packages, interfaces, and type parameters can be resolved across files, and documents include paths, library directories, macro definitions, conversion exclusions, and stdin input.

### 为什么软件包爱好者会关心

sv2v matters to package nerds because it makes an open HDL flow easier to install and automate. A packaged `sv2v` binary lets CI scripts, Makefiles, and Yosys-centered flows consume SystemVerilog projects without requiring proprietary conversion steps.

### 时间线

- 2019: CMU open-hardware collaboration begins, according to the README.
- 2019: Initial public GitHub commit forks Tom Hawkin's Verilog parser.
- 2020: v0.0.1 release is published.
- 2025: v0.0.13 release is published.

### Related projects

- sv2v is related to Yosys, Icarus Verilog, Haskell Stack, Tom Hawkin's Verilog parser, and open hardware build flows that need Verilog output from SystemVerilog sources.

### 来源

- <https://api.github.com/repos/zachjs/sv2v/commits?per_page=1&page=1044>
- <https://api.github.com/repos/zachjs/sv2v/releases?per_page=100>
- <https://github.com/zachjs/sv2v#readme>
- input source_facts.package-manager


## 安全说明

narrow executable package without higher-risk signals.

- **Geiger 风险:** 绿色 / 低
- narrow executable package without higher-risk signals


## Combined YAML source

View the package source record on GitHub. [combined/sv2v.yml](https://github.com/mxcl/pkgdb/blob/main/combined/sv2v.yml)


## 来源

- pkg.so package database
- Geiger risk classifier
- curated package history
- pkgdb category and tag curation
- cross-ecosystem install command graph