# 使用 Homebrew, Nix 安装 surelog

查看 surelog 的安装路径、可执行文件、元数据以及面向 AI 代理工作流的安全说明。

## 安装

```sh
sudo av install brew:surelog
```

其他安装命令:

### macOS

- Homebrew (100%):

```sh
brew install surelog
```

  证据: local Homebrew formula metadata

### Linux

- Nix (92%):

```sh
nix profile install nixpkgs#surelog
```

  证据: nixpkgs package indexes: pkgs/by-name/su/surelog/package.nix from https://api.github.com/repos/NixOS/nixpkgs/git/trees/master?recursive=1

## 软件包事实

- **软件包键:** brew:surelog
- **软件包管理器:** Homebrew
- **版本:** 1.86
- **来源摘要:** SystemVerilog Pre-processor, parser, elaborator, UHDM compiler
- **主页:** <https://github.com/chipsalliance/Surelog>
- **仓库:** <https://github.com/chipsalliance/Surelog>
- **最后更新:** 2026-07-10T03:17:47Z
- **已生成:** 2026-08-03T19:37:03+00:00

## 可执行文件

- surelog (别名)

## 安装行为

- Bottle: 不可用

## 版本和新鲜度

- 页面生成时间: 2026-08-03
- 管理器版本: 1.86
## 项目历史与用法

Surelog is an open-source SystemVerilog 2017 preprocessor, parser, elaborator, and UHDM compiler. Its official README positions it as a reusable front end for open EDA flows rather than a standalone end-user application.

### 项目历史

Surelog's stated goal is to provide a complete SystemVerilog 2017 front end for design and testbench code. The project is part of the CHIPS Alliance ecosystem and is closely tied to UHDM, producing serialized models and VPI-compatible data that downstream tools can consume.

### 采用历史

The README cites equivalence work against large open cores such as BlackParrot and Ariane, and notes Ibex and Earlgrey use in the Surelog/UHDM/Yosys flow. That official evidence places adoption mainly in open-source silicon and EDA toolchain work rather than general application development.

### 使用方式

Surelog is used as a command-line compiler front end and as a library. Users pass Verilog/SystemVerilog source lists, include directories, defines, top modules, cache/output directories, and flow options to generate parsed/elaborated output and UHDM databases.

### 为什么软件包爱好者会关心

Package maintainers care about Surelog because it packages a serious native EDA dependency stack: C++, ANTLR-generated parsing, optional Python APIs, UHDM integration, and command-line compatibility with common Verilog options. It is infrastructure for making open hardware flows installable.

### 时间线

- 2020: Official README links to WOSET 2020 UHDM and Surelog paper/presentation
- Current: README describes SystemVerilog 2017 front-end goals and UHDM output for downstream tools

### Related projects

- Surelog is related to UHDM, Yosys, Verilator-style open EDA flows, and open hardware projects such as Ibex, Earlgrey, Ariane, and BlackParrot.

### 来源

- <https://github.com/chipsalliance/Surelog#readme>
- source_facts.package-manager


## 安全说明

narrow executable package without higher-risk signals.

- **Geiger 风险:** 绿色 / 低
- narrow executable package without higher-risk signals

## 其他软件包管理器记录

- Nix - surelog: normalized package name match | nixpkgs package indexes: pkgs/by-name/su/surelog/package.nix from https://api.github.com/repos/NixOS/nixpkgs/git/trees/master?recursive=1


## Combined YAML source

View the package source record on GitHub. [combined/surelog.yml](https://github.com/mxcl/pkgdb/blob/main/combined/surelog.yml)


## 来源

- pkg.so package database
- Geiger risk classifier
- curated package history
- pkgdb category and tag curation
- external package-manager database matches
- cross-ecosystem install command graph