使用 Homebrew, Nix 安装 surelog

项目链接

• 主页

命令和别名

• surelog

项目历史

Surelog's stated goal is to provide a complete SystemVerilog 2017 front end for design and testbench code. The project is part of the CHIPS Alliance ecosystem and is closely tied to UHDM, producing serialized models and VPI-compatible data that downstream tools can consume.

采用历史

The README cites equivalence work against large open cores such as BlackParrot and Ariane, and notes Ibex and Earlgrey use in the Surelog/UHDM/Yosys flow. That official evidence places adoption mainly in open-source silicon and EDA toolchain work rather than general application development.

使用方式

Surelog is used as a command-line compiler front end and as a library. Users pass Verilog/SystemVerilog source lists, include directories, defines, top modules, cache/output directories, and flow options to generate parsed/elaborated output and UHDM databases.

为什么软件包爱好者会关心

Package maintainers care about Surelog because it packages a serious native EDA dependency stack: C++, ANTLR-generated parsing, optional Python APIs, UHDM integration, and command-line compatibility with common Verilog options. It is infrastructure for making open hardware flows installable.

时间线

• 2020: Official README links to WOSET 2020 UHDM and Surelog paper/presentation
• Current: README describes SystemVerilog 2017 front-end goals and UHDM output for downstream tools

Related projects

• Surelog is related to UHDM, Yosys, Verilator-style open EDA flows, and open hardware projects such as Ibex, Earlgrey, Ariane, and BlackParrot.

来源

• https://github.com/chipsalliance/Surelog#readme
• source_facts.package-manager