# verilator を Homebrew, apk, apt, dnf, MacPorts, Nix, pacman, zypper でインストール verilator のインストール経路、実行ファイル、メタデータ、AI エージェント向けセキュリティノートを確認します。 ## インストール ```sh sudo av install brew:verilator ``` 追加のインストールコマンド: ### macOS - Homebrew (100%): ```sh brew install verilator ``` 証拠: local Homebrew formula metadata - MacPorts (94%): ```sh sudo port install verilator ``` 証拠: MacPorts ports tree: science/verilator/Portfile from https://api.github.com/repos/macports/macports-ports/git/trees/master?recursive=1 ### Linux - apk (92%): ```sh sudo apk add verilator ``` 証拠: Alpine Linux edge package indexes: verilator from https://dl-cdn.alpinelinux.org/alpine/edge/community/x86_64/APKINDEX.tar.gz - Debian apt (92%): ```sh sudo apt install verilator ``` 証拠: Debian stable package indexes: verilator from https://deb.debian.org/debian/dists/stable/main/binary-amd64/Packages.xz - dnf (92%): ```sh sudo dnf install verilator ``` 証拠: Fedora Rawhide package metadata: verilator from https://dl.fedoraproject.org/pub/fedora/linux/development/rawhide/Everything/x86_64/os/repodata/07190dc5ae9f35ae73866675fed6d95fe6e8d9fe22c9d7cdf85862cb2ed24a4c-primary.xml.zst - Nix (92%): ```sh nix profile install nixpkgs#verilator ``` 証拠: nixpkgs package indexes: pkgs/by-name/ve/verilator/package.nix from https://api.github.com/repos/NixOS/nixpkgs/git/trees/master?recursive=1 - pacman (92%): ```sh sudo pacman -S verilator ``` 証拠: Arch Linux sync databases: verilator from https://geo.mirror.pkgbuild.com/extra/os/x86_64/extra.db.tar.gz - zypper (92%): ```sh sudo zypper install verilator ``` 証拠: openSUSE Tumbleweed package metadata: verilator from https://download.opensuse.org/tumbleweed/repo/oss/repodata/50b07339cb64c8ed4091bdbabddadc1ff5737b090e478818a195b40d8a3292861a879139b4a3987c31109699fde9fbf4a716367ddf4eef77da75f96e3193d6ed-primary.xml.zst ## パッケージ情報 - **パッケージキー:** brew:verilator - **パッケージマネージャ:** Homebrew - **バージョン:** 5.050 - **ソース概要:** Verilog simulator - **ホームページ:** - **リポジトリ:** - **最終更新:** 2026-07-02T01:52:21Z - **生成日時:** 2026-08-03T19:37:03+00:00 ## 実行可能ファイル - verilator (エイリアス) - verilator_bin (エイリアス) - verilator_bin_dbg (エイリアス) - verilator_coverage (エイリアス) - verilator_coverage_bin_dbg (エイリアス) - verilator_gantt (エイリアス) - verilator_profcfunc (エイリアス) ## インストール挙動 - Bottle: 利用不可 ## バージョンと鮮度 - ページ生成日: 2026-08-03 - マネージャ版: 5.050 ## プロジェクトの歴史と使われ方 Verilator is an open-source Verilog/SystemVerilog simulator and lint system that compiles HDL into optimized C++ or SystemC models. Its reputation comes from speed: rather than acting like a traditional event-driven simulator, it generates compiled models that are especially useful for large cycle-accurate simulations, CPU models, open hardware projects, and regression farms. ### プロジェクトの歴史 Verilator's roots go back to 1994 at Digital Equipment Corporation, where a Core Logic Group team led by Paul Wasson built technology to convert Verilog to C for Alpha-processor co-simulation. DEC released the source code in 1998, turning the internal tool into available open-source EDA infrastructure. In 2001 Wilson Snyder took up the kit, added a SystemC mode, and packaged it as Verilator2. In 2002 he rewrote the tool from scratch in C++ as Verilator 3.000, producing large performance gains and setting the direction for the modern project under the Veripool umbrella. The project kept expanding SystemVerilog and verification support, including major SystemVerilog and DPI additions in 2009. Verilator 4.000 in 2018 added multithreaded support, a milestone for using commodity multi-core hosts to accelerate hardware simulation. In 2019 Verilator joined the CHIPS Alliance, reflecting its role in the open-source silicon ecosystem. In the Verilator 5 era, the project added a more IEEE-compliant scheduler and delay semantics, addressing historical limitations while preserving its compiled-simulation identity. Current documentation presents it as a fast SystemVerilog simulator, lint tool, C++/SystemC model generator, and JSON-emitting front end for other tools. ### 採用の歴史 Verilator's earliest adoption came from engineering teams that needed fast executable models and were willing to integrate HDL with C++ or SystemC testbenches. Secondary histories and the Verilator FAQ describe use across academic research, open-source projects, major silicon companies, and large organizations such as CERN. The rise of open hardware made Verilator more central. Projects in the RISC-V, OpenRISC, CHIPS Alliance, and education communities use it because it is packageable, automatable, and free software, making it viable in CI where proprietary EDA licensing is impractical or impossible. Commercial adoption grew because Verilator can turn synthesizable RTL into fast simulation artifacts for long regressions and software bring-up. It does not replace every feature of event-driven commercial simulators, but it occupies a powerful niche where speed, openness, and integration with normal C++ tooling matter. ### 使われ方 Package users invoke `verilator` on Verilog or SystemVerilog sources to generate C++ or SystemC, compile the generated model with a C++ testbench, and run the resulting executable. Common flags select C++ output, lint-only checks, tracing, SystemC output, coverage, multithreading, and build integration. Verilator is used for linting RTL, building cycle-accurate simulators for CPU cores and SoCs, running firmware against hardware models, profiling generated simulation code, collecting coverage, and integrating HDL models into larger C++ or SystemC environments. Its companion tools such as `verilator_coverage`, `verilator_gantt`, and profiling helpers support those workflows. ### パッケージ好きにとっての重要性 Verilator is one of the rare EDA tools that feels native to ordinary open-source package workflows: install it, run it in CI, version the RTL and testbench, and avoid license-server friction. For hardware developers, that makes the Homebrew formula more than convenience; it is an on-ramp to serious open silicon verification. ### タイムライン - 1994: DEC's Core Logic Group develops the original Verilog-to-C technology for Alpha co-simulation. - 1998: DEC releases the source code. - 2001: Wilson Snyder packages the technology as Verilator2 and adds SystemC mode. - 2002: Verilator 3.000 is rewritten in C++ with major performance gains. - 2009: Major SystemVerilog and DPI support lands. - 2018: Verilator 4.000 introduces multithreaded support. - 2019: Verilator joins the CHIPS Alliance. - 2022 onward: Verilator 5 work improves IEEE scheduling and delay semantics while retaining the compiled-model architecture. ### Related projects - Verilator is related to Icarus Verilog, CXXRTL/Yosys, GHDL, commercial simulators such as Synopsys VCS, Siemens Questa/ModelSim, and Cadence Xcelium, and open-hardware projects such as OpenRISC and RISC-V cores. Compared with Icarus Verilog it is usually chosen for speed and C++ integration; compared with commercial tools it is chosen for openness and packageability. ### ソース - - - - - - - - - ## セキュリティノート narrow executable package without higher-risk signals. - **Geiger リスク:** グリーン / 低 - narrow executable package without higher-risk signals ## 他のパッケージマネージャ記録 - Debian apt - verilator - 5.032-1+b2: normalized package name match | Debian stable package indexes: verilator from https://deb.debian.org/debian/dists/stable/main/binary-amd64/Packages.xz | fast free Verilog simulator | http://www.veripool.org/wiki/verilator - Nix - verilator: normalized package name match | nixpkgs package indexes: pkgs/by-name/ve/verilator/package.nix from https://api.github.com/repos/NixOS/nixpkgs/git/trees/master?recursive=1 - Ubuntu apt - verilator - 5.020-1: normalized package name match | Ubuntu 24.04 LTS package indexes: verilator from https://archive.ubuntu.com/ubuntu/dists/noble/universe/binary-amd64/Packages.gz | fast free Verilog simulator | http://www.veripool.org/wiki/verilator - apk - verilator - 5.050-r1: normalized package name match | Alpine Linux edge package indexes: verilator from https://dl-cdn.alpinelinux.org/alpine/edge/community/x86_64/APKINDEX.tar.gz | Convert Verilog and SystemVerilog to C++ or SystemC | https://verilator.org - apk - verilator-dev - 5.050-r1: normalized package name match | Alpine Linux edge package indexes: verilator-dev from https://dl-cdn.alpinelinux.org/alpine/edge/community/x86_64/APKINDEX.tar.gz | Convert Verilog and SystemVerilog to C++ or SystemC (development files) | https://verilator.org - apk - verilator-doc - 5.050-r1: normalized package name match | Alpine Linux edge package indexes: verilator-doc from https://dl-cdn.alpinelinux.org/alpine/edge/community/x86_64/APKINDEX.tar.gz | Convert Verilog and SystemVerilog to C++ or SystemC (documentation) | https://verilator.org - dnf - verilator - 5.046-4.fc45: normalized package name match | Fedora Rawhide package metadata: verilator from https://dl.fedoraproject.org/pub/fedora/linux/development/rawhide/Everything/x86_64/os/repodata/07190dc5ae9f35ae73866675fed6d95fe6e8d9fe22c9d7cdf85862cb2ed24a4c-primary.xml.zst | A fast simulator for synthesizable Verilog | https://veripool.org/verilator/ - dnf - verilator-devel - 5.046-4.fc45: normalized package name match | Fedora Rawhide package metadata: verilator-devel from https://dl.fedoraproject.org/pub/fedora/linux/development/rawhide/Everything/x86_64/os/repodata/07190dc5ae9f35ae73866675fed6d95fe6e8d9fe22c9d7cdf85862cb2ed24a4c-primary.xml.zst | Libraries and header files for verilator | https://veripool.org/verilator/ - dnf - verilator-doc - 5.046-4.fc45: normalized package name match | Fedora Rawhide package metadata: verilator-doc from https://dl.fedoraproject.org/pub/fedora/linux/development/rawhide/Everything/x86_64/os/repodata/07190dc5ae9f35ae73866675fed6d95fe6e8d9fe22c9d7cdf85862cb2ed24a4c-primary.xml.zst | Documentation for verilator | https://veripool.org/verilator/ - pacman - verilator - 5.050-1: normalized package name match | Arch Linux sync databases: verilator from https://geo.mirror.pkgbuild.com/extra/os/x86_64/extra.db.tar.gz | The fastest free Verilog HDL simulator | https://www.veripool.org/verilator/ - zypper - verilator - 5.038-1.5: normalized package name match | openSUSE Tumbleweed package metadata: verilator from https://download.opensuse.org/tumbleweed/repo/oss/repodata/50b07339cb64c8ed4091bdbabddadc1ff5737b090e478818a195b40d8a3292861a879139b4a3987c31109699fde9fbf4a716367ddf4eef77da75f96e3193d6ed-primary.xml.zst | Compiling Verilog HDL simulator | https://www.veripool.org/projects/verilator/wiki/Intro - zypper - verilator-devel - 5.038-1.5: normalized package name match | openSUSE Tumbleweed package metadata: verilator-devel from https://download.opensuse.org/tumbleweed/repo/oss/repodata/50b07339cb64c8ed4091bdbabddadc1ff5737b090e478818a195b40d8a3292861a879139b4a3987c31109699fde9fbf4a716367ddf4eef77da75f96e3193d6ed-primary.xml.zst | Verilator library header files | https://www.veripool.org/projects/verilator/wiki/Intro - zypper - verilator-examples - 5.038-1.5: normalized package name match | openSUSE Tumbleweed package metadata: verilator-examples from https://download.opensuse.org/tumbleweed/repo/oss/repodata/50b07339cb64c8ed4091bdbabddadc1ff5737b090e478818a195b40d8a3292861a879139b4a3987c31109699fde9fbf4a716367ddf4eef77da75f96e3193d6ed-primary.xml.zst | Examples for verilator | https://www.veripool.org/projects/verilator/wiki/Intro - MacPorts - verilator: normalized package name match | MacPorts ports tree: science/verilator/Portfile from https://api.github.com/repos/macports/macports-ports/git/trees/master?recursive=1 ## Combined YAML source View the package source record on GitHub. [combined/verilator.yml](https://github.com/mxcl/pkgdb/blob/main/combined/verilator.yml) ## ソース - pkg.so package database - Geiger risk classifier - curated package history - pkgdb category and tag curation - external package-manager database matches - cross-ecosystem install command graph