Installer icarus-verilog avec Homebrew

Liens du projet

• Page d'accueil
• Dépôt

Commandes et alias

• iverilog
• iverilog-vpi
• vvp

Historique du projet

The project README describes Icarus Verilog as a compiler for the IEEE 1364 Verilog HDL, with partial IEEE 1800 SystemVerilog support, and emphasizes that it is a compiler whose generated code is handled by back-end tools rather than a monolithic traditional simulator.

Its source tree carries a 2000-2026 Stephen Williams copyright line, and its release tags span early 0.8/0.9 series tags through v13_0. The documentation site includes user, target, and developer manuals, reflecting a tool that has accumulated both end-user workflows and internal extension points over decades.

Historique d'adoption

Icarus Verilog is widely packaged across Unix-like and developer package ecosystems, including Homebrew, Debian/Ubuntu, Fedora, Arch, Nix, MacPorts, Chocolatey, Scoop, winget, and openSUSE according to the input package metadata. That spread mirrors its role as an accessible simulator for students, hobbyists, CI jobs, and open hardware projects.

Modes d'utilisation

The basic workflow is to compile Verilog sources with `iverilog -o output input.v` and run the compiled result with `vvp output`. The documentation also covers command files for larger designs, root module selection, waveform viewing, VPI modules, multiple code-generation targets, and developer internals.

Pourquoi les passionnés de paquets s'y intéressent

Icarus Verilog is one of the canonical open-source EDA packages: old enough to have autotools-era build expectations, important enough to appear in nearly every serious package set, and small enough to be a default answer when a package manager needs a Verilog simulator for tests or education.

Chronologie

• 2000: Source tree copyright range begins for Stephen Williams's Icarus Verilog codebase.
• 2006: Public tags include v8-s20060822 and the 0.8/0.9 release line.
• 2010s: v10 and v11 tags mark continued evolution of the compiler/runtime toolchain.
• 2020s: v12_0 and v13_0 tags mark later standard-conformance, diagnostics, and runtime stability work.

Related projects

• Related tools and concepts include Verilog HDL, SystemVerilog, IEEE 1364, IEEE 1800, VPI, waveform viewers, open-source EDA flows, and the `vvp` runtime shipped with Icarus Verilog.

Sources

• https://formulae.brew.sh/formula/icarus-verilog
• https://github.com/steveicarus/iverilog
• https://steveicarus.github.io/iverilog/
• https://steveicarus.github.io/iverilog/releases/v13-0-release-note.html
• https://steveicarus.github.io/iverilog/usage/getting_started.html