icestorm mit Homebrew, apk, dnf, Nix installieren

Projektlinks

• Homepage
• Repository

Befehle und Aliase

• icebox_asc2hlc
• icebox_chipdb
• icebox_colbuf
• icebox_diff
• icebox_explain
• icebox_hlc2asc
• icebox_html
• icebox_maps
• icebox_stat
• icebox_vlog
• icebram
• icemulti
• icepack
• icepll
• iceprog
• icetime
• iceunpack

Projektgeschichte

The project began as an effort to document the iCE40 bitstream format and provide simple tools for analyzing and creating bitstream files. Its own timeline records a first public release in March 2015, a working fully open-source flow with Yosys and Arachne-pnr in May 2015, and a move of the source code to GitHub in July 2015.

IceStorm's documentation frames Lattice iCE40 as a good target because the architecture is regular and minimal, with inexpensive development boards available. That made the family useful both for reverse-engineered documentation and as a reference platform for open FPGA tooling.

Adoptionsgeschichte

IceStorm became important because it linked several independent tools into an end-to-end flow: Yosys for synthesis, Arachne-pnr and later nextpnr for place-and-route, IceStorm tools for packing, unpacking, timing, bitstream inspection, and programming. By 2016 the documentation listed support across LP/HX 1K, 4K, and 8K package variants, and in 2018 it added iCE40 UltraPlus support.

The package shows up in Homebrew, Alpine, Fedora, and Nix metadata because FPGA hobbyists, hardware hackers, and digital-design developers often want the flow on ordinary Unix-like developer machines rather than inside vendor IDEs.

Wie es verwendet wird

A typical flow synthesizes Verilog with Yosys, places and routes with Arachne-pnr or nextpnr, packs the ASCII bitstream with `icepack`, and programs hardware with `iceprog`. Other tools such as `iceunpack`, `icebox_explain`, `icebox_vlog`, `icetime`, and `icepll` support reverse engineering, inspection, timing, and PLL configuration.

The package is especially associated with small iCE40 boards such as the iCEstick and HX8K breakout board, where a command-line flow is enough to build, inspect, and upload simple FPGA designs.

Warum Paket-Nerds sich dafür interessieren

Project IceStorm is one of the packages that made open FPGA development feel like normal Unix development: install compiler-like tools, run commands, inspect generated artifacts, and avoid proprietary GUI-only flows for supported iCE40 parts.

It is also historically important as a bridge between software package managers and hardware toolchains. Its executables expose FPGA bitstreams as files that can be packed, unpacked, explained, converted to Verilog, timed, and programmed.

Zeitleiste

• 2015-03-22: First public release and demonstration video.
• 2015-05-27: Working fully open-source flow with Yosys and Arachne-pnr.
• 2015-07-19: 8K chip support released and source code moved to GitHub.
• 2016-01-17: First IceTime timing-analysis release.
• 2016-02-07: Support for all package variants of LP1K, LP4K, LP8K, HX1K, HX4K, and HX8K.
• 2018-01-30: iCE40 UltraPlus support released.
• 2025: The GitHub repository lists v1.1 as a tagged release.

Related projects

• Yosys provides Verilog synthesis for the iCE40 flow.
• Arachne-pnr and nextpnr provide place-and-route options used with IceStorm.
• Lattice iCEcube2 is the proprietary tool whose generated bitstreams were used as comparison material during reverse engineering.
• F4PGA and other FPGA documentation efforts belong to the broader open FPGA tooling movement.

Quellen

• https://formulae.brew.sh/formula/icestorm
• https://github.com/YosysHQ/icestorm
• https://github.com/YosysHQ/icestorm/releases
• https://prjicestorm.readthedocs.io/en/latest/overview.html